1. Field of the Invention
This invention relates to computer memory technology, and more particularly, to an embedded memory control circuit for use in conjunction with a memory module consisting of two or more memory chips for the purpose of suppressing the defective banks in the memory module, if any, and combining the nondefective banks into a single memory unit.
2. Description of Related Art
In the manufacture of computer memory devices, the manufactured memory circuitry may contain defective parts that would be unusable for data storage. A conventional solution to this problem is to provide redundant circuitry that can be utilized as substitute for the defective parts of the manufactured memory device, thereby making the overall memory device nevertheless usable for data storage. One drawback to this solution, however, is that when the defective part of a memory device is more than the redundant circuitry can substitute, the memory device is unusable and therefore should be discarded, resulting in a low yield rate and an increase in the overall manufacture cost.
Still one solution to the above-mentioned problem is to use a complementary set of memory chips in such a manner that one defective bank in one memory chip can be functionally replaced by one nondefective bank in another memory chip. A realization of this solution is to use a so-called ASIC (Application-Specific Integrated Circuit) controller in conjunction with a number of partly-defective memory chips, so that the nondefective banks in these memory chips can be combined as a single memory unit. One drawback to this solution, however, is that it would cause a considerable signal delay; and this signal delay would cause erroneous data when the ASIC controller is used in a high-speed environment. Moreover, the incorporation of the ASIC controller in the memory module would require a new design to the layout of the memory module, and therefore would result in an increase in the overall manufacture cost. The use of the ASIC controller is therefore undesired.